Power supplies and power converters are used in a variety of electronic systems. Electrical power is generally transmitted over long distances as an alternating current (AC) signal. The AC signal is divided and metered as desired for each business or home location, and is often converted to direct current (DC) for use with individual electronic devices or components. Modern electronic systems often employ devices or components designed to operate using different DC voltages.
One type of power converter is referred to as a multi-level converter because more than two voltage levels are used to generate an output voltage. As a general rule, multi-level converters step-up to or step-down from a certain voltage using smaller discrete stages. There are numerous multi-level converter topologies, where different topologies vary with regard to efficiency, complexity, and ease of miniaturization (e.g., forming a multi-level converter using integrated circuits). In some examples, a multi-level converter includes a network of switches and capacitors, as well as a control mechanism for the switches. When the switches are power transistors, the control circuit can be referred to as a gate driver circuit, which can be a discrete circuit, a partially integrated circuit, or a fully integrated circuit (IC).
FIG. 1 shows a prior art cascaded bootstrap gate driver circuit for a multi-level converter. In the multilevel converter of FIG. 1, QTN, QT2, QT1, and QL are power transistors; DBN, DB2, DB1 are bootstrap diodes; RDBN, RDB2, RDB1 are bootstrap resistors; CBN, CB2, CB1 are bootstrap capacitors; and VDR is the gate driver power supply voltage (e.g., 5 V in FIG. 1); CD is a decoupling capacitor(s); D1-DN are non-ground referenced gate drivers; DL is a ground referenced gate driver that does not require level shift or bootstrapping; and VBUS is the power supply voltage source.
The operation of the cascaded gate driver circuit of FIG. 1 includes various charging periods represented by dashed loops 102, 104, and 106. In charging period 1, QL is on and CB1 is charged by VDR to VCB1≈VDR−VDB1−VRDB1≈4.5 V (assuming VRDBX≈0 V and VDBX≈0.5 V). In charging period 2, QT1 is on and CB2 is charged by CB1 to VCB2≈VCB1−VDB2−VRDB2≈4.0 V. In charging period N, QTN-1 is on and CBN is charged by CBN-1 to VCBN≈VCBN-1−VDBN−VRDBN≈VDR−N(VRDBN+VDBN). If N=3, VCB3≈3.5 V. If N=4, VCB≈3.0 V. For the gate driver circuit of FIG. 1, a diode drop occurs during each charging period. Thus, as the number of levels increases, the subsequent bootstrap capacitor voltage in the charging sequence decreases. This drop in voltage in each subsequent stage limits the number of levels that can be supported. Accordingly, a need exists for a cascaded bootstrap supply circuit with a reduced voltage drop between the cascaded bootstrap capacitors.